Physical Design Engineer, Forward Deployed Engineering

About the Team

OpenAI’s Forward Deployed Engineering team partners with leading semiconductor companies to deploy production-grade AI systems across the entire chip design lifecycle: design, verification, and physical design. We operate at the intersection of customer delivery and core platform development, embedding deeply with customers to translate frontier model capabilities into systems that materially improve engineering workflows and accelerate innovation.

Our work turns early, high-touch deployments into repeatable solution patterns, reference architectures, and evaluation practices that scale across the semiconductor ecosystem.

About the Role

We are seeking a highly skilled Physical Design Engineer to join our semiconductor-focused Forward Deployed Engineering team. This is a senior IC role that will begin with a strong emphasis on physical design expertise, technical judgment, advisory leverage, and customer credibility, with the expectation that the person will grow into a broader Forward Deployed Engineering role over time.

In the near term, you will serve as the team’s physical design SME across semiconductor deployments: helping FDEs, Product, and Research understand backend implementation workflows, pressure-test AI-assisted solution ideas against real physical design constraints, and raise the quality of our customer-facing technical work. You will help the broader team build fluency in implementation flows, EDA tooling, signoff methodology, and the trade-offs that shape physical design decisions in practice.

Over time, we expect this role to expand beyond SME support into broader FDE ownership: partnering directly with customers, shaping deployment strategy, building and iterating production-grade AI systems, driving technical workstreams, and helping turn high-touch semiconductor deployments into repeatable solutions.

This is a strong fit for someone who brings deep physical design expertise today and is excited to grow into a customer-facing, systems-building, delivery-oriented FDE role.

In this role, you will:

Serve as the physical design SME for semiconductor customer engagements, helping FDE teams understand backend implementation workflows, constraints, and opportunities

Partner with FDEs during customer discovery and scoping to translate ambiguous pain points into clear solution hypotheses, success criteria, and technical plans

Support customer-facing technical conversations as a trusted advisor, engaging credibly with technical leaders

Help shape AI-assisted solutions across physical design workflows, including floorplanning, place and route, clocking, timing closure, congestion, power, physical verification, and signoff

Guide feasibility and integration decisions across the entire chip design lifecycle: design, verification, and physical design

Partner with FDEs and customer SMEs to curate evaluation datasets, golden tasks, rubrics, and acceptance criteria for physical design use cases, ensuring evals reflect real workflows and meaningful success metrics

Build or guide lightweight prototypes, benchmarks, methodology experiments, and internal tools that validate opportunities and accelerate solution development

Educate and mentor the broader FDE team on physical design concepts, implementation flows, EDA tooling, and key trade-offs so the org can engage customers with greater depth and confidence

Surface repeated customer signal to Product and Research to help shape roadmap, model behavior, and platform capabilities for semiconductor use cases

Progressively take on broader FDE responsibilities, including customer discovery, solution architecture, prototype development, production deployment, and ownership of technical workstreams

Minimum Qualifications

BS with 7+ years, MS with 5+ years, or equivalent industry experience in physical design, physical implementation, or backend signoff for complex ASIC or SoC programs

Demonstrated success bringing complex designs through tapeout, with hands-on experience in floorplanning, place and route, CTS, timing closure, power analysis, physical verification, and signoff

Deep familiarity with industry-standard EDA tools and flows for synthesis, PNR, STA, physical verification, equivalence checking, and power analysis

Strong understanding of how physical design intersects with microarchitecture, RTL, verification, design methodology, libraries/PDKs, and system-level PPA trade-offs