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Senior ASIC RTL Design Engineer, AI Hardware

Hybrid

Part remote, part office, you need to live within commuting distance of a named location.

Hybrid · Sunnyvale, CA

Employer listed it 3 weeks ago · Added 5 weeks ago

Been open since 5 weeks ago, still being checked, but it has been live a while.

Salary

$200k to $290k per year

Location

Hybrid · Sunnyvale, CA

Timezone

Not stated

Contract

Full-time

Experience

Senior

Category

Software

Stated by the employer in the job description

What the advert says

Quoted word for word from the employer's advert. Where it says nothing, we say so.

Working hours
Not mentioned in the advert
Where you can work from
Can work in a hybrid work environment.
Contract
Not mentioned in the advert
Experience asked for
8+ years of experience in delivering complex, high performance high quality RTL designs.
Pay
The base salary range for this position is $200,000 to $290,000 annually.

Remote flexibility

Hybrid

This role is only partly remote, the employer expects time in the office around Sunnyvale, CA, Hybrid, so you need to live within commuting distance.

What the employer says

  • Source listing states candidate location: "Sunnyvale, CA, Hybrid"
  • Listing mentions "Hybrid"

What Nomaders makes of it

  • Not suitable if you plan to move between countries

The quotes above are the employer's own words; the reading is ours. Always check the original listing and employment terms before working from another country.

Before you apply

Experience: employer states

Written as a nice-to-have

  • “Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.”

Questions worth asking: Nomaders interpretation

  • This role involves office time, but the advert does not say how often. Ask how many days a week are expected on site.
  • The advert does not say whether this is employment or a contractor arrangement. Ask, as it affects tax and benefits.

Produced automatically from this advert's text; not reviewed by a person. The employer's own page is the final word.

About the role

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

About The Role:

As a senior front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.

Responsibilities:

Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.

Work closely with PD team members for design closure to meet PPA goals.

Work closely with Design verification and DFT teams for achieving the best functional and test coverage.

Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.

Debug silicon-level functional, timing, and power issues during bring up.

Requirements

Master’s degree in Computer Science, Electrical Engineering, or equivalent.

Can work in a hybrid work environment.

8+ years of experience in delivering complex, high performance high quality RTL designs.

Experience with Front End Chip integration and third-party IP integration.

Demonstrated experience in high-performance computing, GPU/CPU designs, machine learning or related fields.

Proven track record of multiple silicon success.

Experience collaborating with external vendors.

Networking stack experience including TCP/IP, RDMA and Ethernet.

Knowledge of PCIe, CPU interfaces and Serdes technology.

Working knowledge of scripting tools : Python, TCL.

Assets:

Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.

Experience managing external ASIC vendor through product development cycle.

Location: Sunnyvale, CA (Open to Remote)

Requirements

  • ·Master’s degree in Computer Science, Electrical Engineering, or equivalent.
  • ·Can work in a hybrid work environment.
  • ·8+ years of experience in delivering complex, high performance high quality RTL designs.
  • ·Experience with Front End Chip integration and third-party IP integration.
  • ·Demonstrated experience in high-performance computing, GPU/CPU designs, machine learning or related fields.

Benefits

No benefits package published with this listing. Ask about it at first interview.

How to apply

  1. 1Check the flexibility label above, hybrid, matches where you plan to live and work.
  2. 2Tailor your CV to the role at Cerebras, mentioning your remote working experience.
  3. 3Apply directly on the employer's careers page using the button below. Nomaders never handles your application.

Found 1mo ago. Last checked today. Always confirm the details on the original posting, salary and location can change after publication.

Listing sourced from Company boards.

$200k to $290k per year · You'll be taken to the employer's careers page.